Principal Application Engineer
Cadence Design Systems, Inc., Bracknell, Bracknell Forest
Principal Application Engineer
Salary Not Specified
Cadence Design Systems, Inc., Bracknell, Bracknell Forest
- Full time
- Permanent
- Onsite working
Posted 2 weeks ago, 6 Nov | Get your application in now before you miss out!
Closing date: Closing date not specified
job Ref: 6a5a436efe9b477cbff6f528e2ae58c3
Full Job Description
As an integral member of the Formal verification application engineering team, you will work with industry leading semiconductor and system companies to deploy Cadence's market leading Jasper Formal Verification products. You will work with the EMEA based AE and sales teams to provide technical support in the Pre and Post-Sales process. In this pivotal role the you will be a front-line contact with Cadence customer's engineers and CAD teams and will the following responsibilities: · · Providing technical support for the deployment of Cadence's market leading Jasper Formal Verification products; · Working with the various Cadence sales teams and product developers to develop innovative solutions to address customer's challenging problems; · Providing proactive support and problem consultation to make our product users successful; · Collaborating with R&D to introduce new formal flows and Apps to customers; · Championing customer needs and helping R&D to develop competitive and creative technical solutions; · Understanding the competitive landscape and continuously working on differentiating Cadence's solutions; · Fostering a collaborative, team-oriented, work environment; · Representing Cadence at technical conferences and trade shows; · Applying formal property checking tools to diverse functional verification problems. · Deliver training course for formal verification technology · Lead projects and initiatives The position will include travel to customer sites and involve significant interaction with customers.
- BEng in Electronic / Micro-Electronic Engineering or Computer Science - or equivalent
- Experience in using formal verification tools.
- Experience of Hardware Design and Verification languages including PSL, SV Verilog, VHDL, System Verilog, System-C, TLM.
- Experience of the IP/ Soc verification process.
- Experience with Unix / Linux environment including scripting languages.
- Good Communication skills We're doing work that matters. Help us solve what others can't.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a candidate to be part of its Formal verification application engineering team . If you like to architect and develop solutions for challenging problems in a fast and innovative paced environment, using state of the art technology this is a great opportunity., Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
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